Current process technology allows an output driver to generate rapid changes in output voltage. Fast transitions are desirable, but can lead to unwanted noise on internal power and ground busses. Since power and ground busses are coupled to internal logic signals, noise on the power and ground busses may cause erroneous states to be generated in the internal logic signals. Fast transitions can also cause ringing on the output pin signal, which may cause erroneous data to appear in a receiving device being driven by the output pin signal.
The fundamental cause of noise on the power and ground busses is due to the transition of the voltage level driving the load. FIG. 1 shows an output driver circuit 101 in combination with an output load device 106 driven through pad 105 and inductive elements 102 and 107 internal to the integrated circuit and additional inductive elements 103 and 108 comprising bond pads and wires connected to positive and negative power supplies, and printed circuit traces 104 and 109 external to the integrated circuit device. When the pad signal is a logical 1, transistor 101a is on, and a current i.sub.TR flows from the positive power supply through trace 104, bond wire 103, integrated circuit power line 102, transistor 101a, pad 105, to load 106. When transistor 101a suddenly shuts off, the induction of elements 104, 103, and 102 causes a voltage buildup, allowing VCC.sub.INT, the internal power supply voltage, to be greater than VCC.sub.EXT, the external power supply voltage. At this point, load 106 is at a positive voltage level, for example 5 volts. When transistor 101b suddenly turns on and current i.sub.TF begins to flow, the inductance of elements 107, 108, and 109 limits current flow and causes a voltage buildup across elements 107, 108, and 109, allowing VSS.sub.ISNT to be greater than VSS.sub.EXT. Opposite variations in VCC and VSS occur due to opposite transitions of transistors 101a and 101b. When multiple transistors equivalent to transistors 101a and 101b switch simultaneously, the voltage variations on the power and ground busses can be unacceptably large, causing erroneous data to be generated internally. Erroneous data can also be generated at the load device in response to a fast transition.
Prior efforts to control power and ground bounce (variation in VCC and VSS voltages) have included a staged turn-on technique, a ramped pre-drive technique and a feedback circuit. These are now discussed.
FIG. 2A shows a prior art circuit for reducing variation in VCC and VSS levels by generating parallel drive signals with different delays in response to an unbuffered output signal. As shown in FIG. 2A, in the staged turn-on technique, the output driver is formed as a number of smaller drivers 203, 205, and 207 placed in parallel between VCC and VSS. Delay devices 204 and 206 cause delays to the driving signal on line 202 so that drivers 203, 205, and 207 switch at slightly different times, causing a more gradual voltage change at pad 208.
FIG. 2B shows a circuit which provides a ramped pre-drive. Weak pre-driver inverter 212 has a relatively small channel width and responds relatively slowly to a switching input signal. Thus driver 214 switches more slowly and therefore causes less bounce in VCC and VSS.
FIG. 2C shows an output driver with feedback to VCC and VSS. Resistors 223 and 225 limit current flow to and from pad 226. The feedback occurs because, for example, when the gate-to-source voltage difference at transistor 224b is high, transistor 224b is hard on. But a high current i from pad 226 through resistor 225 to VSS raises the voltage at the source of transistor 224b, turning transistor 224b partly off. As the voltage on pad 226 approaches the VSS voltage, current through resistor 225 decreases, so the source voltage of transistor 224b decreases, transistor 224b turns more on, and current continues to flow. A similar effect happens with resistor 223 and transistor 224a.
None of these prior art devices eliminates the ground bounce which occurs at the end of a switching transition.